Memory system designers often consider a variety of criteria in determining an optimum design for a given memory application. For example, system bandwidth is often constrained by allowable pin counts (interface widths) and achievable link data rates.
Total system bandwidth is often expressed in terms of an interface width N (representing the number of links that connect a memory controller to a memory device) multiplied by individual link rate R (representing a number of bits transferred per second over a link). Designers sometimes achieve a desired total bandwidth in different configurations for a given system architecture by, for example, halving widths and correspondingly doubling link data rates and vice-versa. This corresponds to a ratio between available core I/O paths (on the order of a power-of-two value in the thousands) and the designed number of interface links. The ratio generally corresponds to a power-of-two integer (2N) value because of the binary nature of integrated circuit devices.
While implementing power-of-two relationships in pin counts and link data rates can be straightforward, practical application of this formula is limited by signal integrity issues associated with high-volume and low-cost packaging interconnects. In other words, simply doubling a data rate while halving the number of interface links may not be possible without new and costly packaging technologies.
Thus, the need exists for a way to provide designers with the ability to independently configure core and interface data rates for memory system integrated circuit devices.